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A digital architecture for support vector machines: theory, algorithm, and FPGA implementation.

D Anguita1, A Boni, S Ridella

  • 1Dept. of Biophys. and Electron. Eng., Univ. of Genova, Genoa, Italy.

IEEE Transactions on Neural Networks
|February 5, 2008
PubMed
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This paper introduces a novel digital architecture for Support Vector Machine (SVM) learning on Field Programmable Gate Arrays (FPGAs). The new algorithm demonstrates improved robustness against quantization errors for real-time classification tasks.

Area of Science:

  • Digital Signal Processing
  • Machine Learning Hardware Acceleration

Background:

  • Support Vector Machines (SVMs) are powerful classification algorithms.
  • Implementing SVMs on hardware, particularly Field Programmable Gate Arrays (FPGAs), presents challenges due to quantization effects and computational complexity.
  • Existing SVM learning algorithms can be sensitive to quantization errors in fixed-point implementations.

Purpose of the Study:

  • To propose a novel digital architecture for efficient Support Vector Machine (SVM) learning on FPGAs.
  • To develop a new SVM learning algorithm that is robust to quantization errors.
  • To demonstrate the effectiveness of the proposed architecture and algorithm on a real-world application.

Main Methods:

  • A new SVM learning algorithm comprising a recurrent network for parameter estimation and a bisection process for threshold computation.

Related Experiment Videos

  • Design and implementation of a digital architecture for the proposed SVM learning algorithm.
  • Mapping the architecture onto a Xilinx Virtex II FPGA.
  • Performance evaluation using a channel equalization problem.

    • Main Results:

    • The proposed SVM architecture shows robustness to quantization effects in the feedforward phase.
    • The new SVM learning algorithm is less sensitive to quantization errors compared to existing methods.
    • The implemented architecture achieves effective performance on a channel equalization task, highlighting real-time capabilities.

    Conclusions:

    • The developed digital architecture and novel algorithm provide an efficient and robust solution for SVM learning on FPGAs.
    • The approach is suitable for applications requiring real-time processing and is resilient to fixed-point arithmetic limitations.
    • This work contributes to the advancement of hardware-accelerated machine learning.