Design and implementation of a random neural network routing engine.

Area of Science:

• Artificial Intelligence
• Computer Engineering
• Network Architecture

Background:

• Random Neural Network (RNN) models are analytically tractable and widely used in software.
• Cognitive Packet Networks (CPN) offer a routing table-free architecture utilizing RNN-based reinforcement learning.
• Existing RNN software implementations face limitations for real-time network processing.

Purpose of the Study:

• To present the first hardware implementation of the Random Neural Network (RNN) model.
• To detail the design of the Smart Packet Processor (SPP) for CPN routing.
• To introduce algorithmic modifications for improved RNN efficiency in hardware.

Main Methods:

• Hardware implementation of the RNN model on a custom chip, the Smart Packet Processor (SPP).
• Modification of the RNN reinforcement learning algorithm to reduce weight terms from 2n² to 2n.
• Design of a dual-port device (SPP) with dual access memory and optimized output calculation modules.
• Simulations to validate the SPP design in isolated and networked environments.

Main Results:

• Successful hardware implementation of the RNN model in the SPP.
• Significant memory savings and simplified steady-state probability calculations due to algorithmic modification.
• Demonstrated functionality of the SPP for RNN-based routing in CPN.

Conclusions:

• The hardware implementation of RNNs via the SPP offers significant advantages over software approaches for CPN.
• The modified reinforcement learning algorithm enhances efficiency and reduces resource requirements.
• This work paves the way for practical, hardware-accelerated CPNs.