A four-quadrant subthreshold mode multiplier for analog neural-network applications.

Area of Science:

• Electronics and Electrical Engineering
• Microelectronics
• Analog Circuit Design

Background:

• Analog multipliers are fundamental building blocks in signal processing and control systems.
• Subthreshold operation in CMOS devices offers advantages in low power consumption, crucial for VLSI applications.
• Existing analog multiplier designs often face challenges in achieving high accuracy and low power simultaneously.

Purpose of the Study:

• To introduce a new four-quadrant CMOS analog multiplier circuit.
• To enable the design of efficient very large scale integration (VLSI) analog neural networks.
• To demonstrate the feasibility and functionality of the proposed multiplier design.

Main Methods:

• Implementation of a cross-coupled quad structure utilizing CMOS devices operating in subthreshold mode.
• Differential multiplication achieved by controlling gate and bulk terminals.
• Experimental validation using transistor arrays and network simulations with 11 neurons and 31 synapses.

Main Results:

• The proposed multiplier exhibits characteristics suitable for VLSI analog neural network design.
• Reasonable operational speed is achieved despite subthreshold current levels due to small voltage swings (few V(t)).
• Simulation studies confirm a useful level of functionality for the multiplier within a neural network context.

Conclusions:

• The novel subthreshold CMOS analog multiplier provides a viable solution for low-power, high-density analog neural network implementations.
• The design offers a balance between performance and power efficiency for VLSI applications.
• Experimental and simulation results validate the practical utility of the proposed multiplier circuit.