A single 1.5-V digital chip for a 10(6) synapse neural network.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Microelectronics

Background:

• Advancements in artificial intelligence necessitate efficient hardware for neural network processing.
• Existing hardware often faces limitations in power consumption and portability for large-scale neural networks.

Purpose of the Study:

• To propose a novel digital-chip architecture for a 10^6-synapse neural network.
• To enable low-power, high-speed operation suitable for portable equipment.

Main Methods:

• Development of a digital-chip architecture featuring an on-chip DRAM cell array for synapse weights.
• Implementation of a pitch-matched interconnection and combinational unit circuit for efficient layout.
• Utilizing dynamic data transfer circuits and 1.5-V operation to minimize power dissipation.

Main Results:

• The proposed architecture achieves an estimated power dissipation of 75 mW.
• Predicted processing speed reaches 1.37 giga connections per second at 1.5-V supply.
• A scaled-down version with an 8-kb DRAM cell array was successfully fabricated and operated.

Conclusions:

• The digital-chip architecture offers a viable solution for high-performance, low-power neural network processing in portable applications.
• Integration of memory and processing circuits on a compact chip is feasible using standard CMOS technology.
• The demonstrated functionality confirms the potential of this architecture for future neuromorphic computing systems.