A CMOS analog adaptive BAM with on-chip learning and weight refreshing

Area of Science:

• Analog computing
• Neuromorphic engineering
• Integrated circuit design

Background:

• The transconductance-mode (T-mode) approach enables analog neural network hardware.
• On-chip learning and weight storage are crucial for robust neural hardware.
• Device mismatches can impact the performance of analog neural networks.

Purpose of the Study:

• To extend the T-mode approach for on-chip Hebbian learning and analog weight storage.
• To evaluate the impact of learning circuit mismatches on neural network performance.
• To validate theoretical predictions with experimental results.

Main Methods:

• Implementation of a 5+5-neuron bidirectional associative memory (BAM) prototype using a standard CMOS process.
• Theoretical computation and Monte Carlo HSPICE simulations to estimate transistor mismatch effects.
• Experimental verification using the fabricated BAM prototype.

Main Results:

• On-chip Hebbian learning and analog weight storage were successfully demonstrated.
• Transistor mismatches in learning circuits were quantified and their impact assessed.
• Theoretical predictions of mismatch effects were validated by experimental measurements.

Conclusions:

• The T-mode approach effectively supports on-chip Hebbian learning in analog neural networks.
• While on-chip learning can compensate for some nonidealities, learning circuit mismatches require careful consideration.
• The study confirms the feasibility and validates the performance of the proposed analog neural network hardware.