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A neural network learning algorithm tailored for VLSI implementation.

P W Hollis1, J J Paulos

  • 1Microprocessor and Memory Technol. Group, Motorola Inc., Austin, TX.

IEEE Transactions on Neural Networks
|January 1, 1994
PubMed
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This study optimizes on-chip learning for VLSI neural networks using novel techniques. These methods enhance learning speed and accuracy in hardware implementations, paving the way for efficient artificial intelligence.

Area of Science:

  • Electrical Engineering
  • Computer Science
  • Artificial Intelligence

Background:

  • VLSI neural networks require efficient on-chip learning algorithms.
  • Conventional technologies present challenges for implementing complex learning processes.

Purpose of the Study:

  • To present optimization concepts for on-chip learning algorithms in VLSI neural networks.
  • To improve the efficiency and effectiveness of hardware-based neural network training.

Main Methods:

  • Utilized a semi-parallel perturbation learning approach for accelerated hidden-layer updates.
  • Implemented an infinity-norm error measure for simplified error detection.
  • Employed dynamic gain adaptation and an annealed learning rate for consistent convergence.
  • Incorporated logarithmic analog-to-digital conversion to eliminate digital multipliers during backpropagation.

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Main Results:

  • Achieved consistent convergence and maximized effective resolution of bounded weights.
  • Demonstrated that logarithmic analog-to-digital conversion maintains learning quality without digital multipliers.
  • Validated the proposed concepts through simulations of continuous mapping problems.

Conclusions:

  • The described concepts offer a viable approach to optimizing on-chip learning for VLSI neural networks.
  • These optimizations are compatible with conventional VLSI technologies.
  • The methods contribute to the development of more efficient and effective hardware for artificial intelligence.