Optimal usage of available wiring resources in diffractive-reflective optoelectronic multichip modules

Area of Science:

• Computer Engineering
• Electrical Engineering
• Materials Science

Background:

• VLSI and optoelectronic multichip module technologies enable ultracompact, massively parallel processing systems.
• Technological parameters significantly influence wirability and delay characteristics, impacting system architecture.

Purpose of the Study:

• To present an analytical model for design space exploration of interconnection networks in multinode chips on a single multichip module substrate.
• To evaluate system designs using a two-level interconnect with k-ary-n-cube networks for interchip and intrachip communication.

Main Methods:

• Development of an analytical model for interconnection network design space exploration.
• Evaluation of system designs with a two-level interconnect structure.
• Analysis of k-ary-n-cube networks for interchip and intrachip communication.

Main Results:

• The study analyzes the impact of architectural and technological parameters on network implementation.
• Optimal network implementation is determined based on average no-load latency.
• Design space exploration identifies trade-offs in network performance.

Conclusions:

• Technological and architectural parameters are critical for optimizing interconnection networks in parallel processing systems.
• The presented model facilitates informed design decisions for ultracompact systems.
• Understanding latency impacts is key to efficient network implementation.