Low energy, low latency and high speed array divider circuit using a shannon theorem based adder cell.

Area of Science:

• Digital circuit design
• VLSI (Very Large Scale Integration) design
• Computer arithmetic

Background:

• Full adders are fundamental components in digital systems, crucial for arithmetic operations.
• Divider circuits, essential for computation, rely on efficient adder implementations.
• Existing adder designs present trade-offs in power, speed, and latency.

Purpose of the Study:

• To design and evaluate a novel 1-bit full adder circuit utilizing Shannon theorem.
• To integrate the proposed full adder into Non-Restoring and Restoring divider circuits.
• To compare the performance of the Shannon-based divider with conventional designs.

Main Methods:

• Circuit schematics designed using DSCH2 CAD tool.
• Layout generation performed with Microwind 3 VLSI CAD tool.
• Standard CMOS 0.35 micrometer technology and 3.5 V power supply utilized.
• BSIM 4 analysis for parameter evaluation.
• Comparative analysis against CPL and CMOS adder cell based divider circuits.

Main Results:

• The Shannon-based divider circuit demonstrates lower power dissipation.
• Faster response times and reduced latency were observed.
• Lower energy-per-instruction (EPI) and higher throughput achieved.
• Performance validated against published results.

Conclusions:

• The proposed 1-bit full adder based on Shannon theorem offers superior performance metrics.
• This design provides a more efficient component for implementing divider circuits.
• The findings suggest a promising alternative for low-power, high-speed digital arithmetic.