VLSI architecture of leading eigenvector generation for on-chip principal component analysis spike sorting system

Area of Science:

• Neuroscience
• Electrical Engineering
• Computer Engineering

Background:

• High-density microelectrode arrays in neural recording generate significant data, creating bandwidth bottlenecks.
• On-chip spike detection and principal component analysis (PCA) sorting hardware are crucial for efficient neural data processing.

Purpose of the Study:

• To propose and design the first leading eigenvector generator, a key hardware module for PCA-based spike sorting.
• To enable a low-cost, low-power integrated multi-channel neural recording system.

Main Methods:

• Developed a novel flipped structure for the leading eigenvector generator based on an iterative eigenvector distilling algorithm.
• Implemented an adaptive level shifting scheme to optimize accuracy and area trade-offs.
• Utilized a 90 nm 1P9M CMOS process for hardware implementation.

Main Results:

• The proposed hardware achieves efficient PCA sorting by eliminating division and square root operations.
• The system can train 312 channels per minute at 1MHz operation frequency, processing 32 samples/spike with nine bits/sample.
• Demonstrated low power consumption (282 microwatts) and small silicon area (0.13 mm²).

Conclusions:

• The developed leading eigenvector generator is a key enabler for efficient on-chip PCA-based spike sorting in neural recording systems.
• The proposed hardware design offers a significant reduction in power consumption and silicon area, addressing critical implementation challenges.