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Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

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High-density crossbar arrays based on a Si memristive system.

Sung Hyun Jo¹, Kuk-Hwan Kim, Wei Lu

¹Department of Electrical Engineering and Computer Science, the University of Michigan, Ann Arbor, Michigan 48109, USA.

|February 12, 2009

Summary

We developed large-scale silicon memristive crossbar arrays for memory applications. These arrays show high yield and reliability, enabling future hybrid nano/CMOS systems.

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Area of Science:

Materials Science and Engineering
Electrical Engineering
Nanotechnology

Background:

The development of high-density memory arrays is crucial for advancing computing technologies.
Memristive systems offer promising characteristics for next-generation memory devices due to their non-volatility and scalability.

Purpose of the Study:

To demonstrate the fabrication and functionality of large-scale, high-density crossbar arrays using a silicon-based memristive system.
To evaluate the performance metrics, including yield, ON/OFF ratio, reproducibility, and reliability of the memristive crossbar arrays.
To explore the potential applications of these arrays as resistive random-access memory (RRAM) or write-once memory.

Main Methods:

Fabrication of two-terminal hysteretic resistive switches (memristive devices) at each crosspoint of a 1 kb crossbar array.
Utilized a silicon-based memristive system for device integration.
Characterization of device performance, including addressing capability, ON/OFF ratio, and operational reliability.

Main Results:

Successful demonstration of large-scale (1 kb) high-density crossbar arrays with high yield.
Memristive devices exhibited a high ON/OFF ratio and reliable switching behavior.
The crossbar arrays demonstrated excellent reproducibility and reliability across multiple configurations.

Conclusions:

Silicon-based memristive crossbar arrays are feasible for large-scale integration, offering high performance and reliability.
These arrays can be configured as either resistive random-access memory (RRAM) or write-once memory.
The successful demonstration paves the way for further research into hybrid nano/CMOS systems incorporating these memristive arrays.