Integratable nanowire transistors.

Area of Science:

• Nanotechnology
• Materials Science
• Semiconductor Physics

Background:

• Precise control over nanowire growth is crucial for advanced semiconductor devices.
• Existing methods often lack the ability to dictate both location and direction of nanowire growth.
• Silicon-on-insulator (SOI) substrates are widely used in microelectronics fabrication.

Purpose of the Study:

• To engineer a structure that controls nanowire location and growth direction.
• To demonstrate the fabrication of top-gated metal-oxide-semiconductor field-effect transistors (MOSFETs) using this controlled growth structure.
• To characterize the performance of the fabricated MOSFETs.

Main Methods:

• Engineered a specific structure to guide nanowire growth against an oxide surface.
• Utilized a (001) silicon-on-insulator substrate for device fabrication.
• Grew nanowires in specific crystallographic directions, primarily (110).

Main Results:

• Achieved controlled nanowire growth in terms of location and direction.
• Fabricated top-gated MOSFETs with high performance.
• Demonstrated an impressive Io/Ioff ratio of approximately 10^4.
• Obtained a subthreshold slope of approximately 155 mV/decade.

Conclusions:

• The developed structure effectively controls nanowire growth for device applications.
• The fabricated MOSFETs exhibit excellent electrical characteristics, suitable for integrated circuits.
• Nanowire growth, even when directed, incorporates specific crystallographic planes ({111}) during the addition process.