Enabling cutting-edge semiconductor simulation through grid technology.

Area of Science:

• Semiconductor physics and materials science
• Computational engineering and high-performance computing

Background:

• The global semiconductor industry relies on the continuous scaling of complementary metal oxide semiconductor (CMOS) transistors.
• Scaling introduces statistical variations, posing fundamental challenges for chip and systems designers.
• Understanding transistor behavior is critical for overcoming these design hurdles.

Purpose of the Study:

• To outline recent scientific results from the nanoCMOS project.
• To detail how scientific objectives were implemented using grid-based e-Infrastructure.
• To provide in-depth insight into the physical processes governing scaled transistors.

Main Methods:

• Simulation of over 200,000 complementary metal oxide semiconductor (CMOS) transistors.
• Utilizing grid technology for large-scale, detailed analysis.
• Examining statistical variations introduced by transistor scaling.

Main Results:

• Unprecedentedly detailed examination of statistical variations in scaled transistors.
• Comprehensive insight into the underlying physical processes.
• Successful application of grid-based e-Infrastructure to address complex scientific goals.

Conclusions:

• Grid technology is essential for analyzing the complexities of modern semiconductor scaling.
• The nanoCMOS project successfully leveraged e-Infrastructure to gain deep insights into transistor behavior.
• This work supports overcoming fundamental challenges in advanced chip and systems design.