Prechirper to relax the timing restrictions for soliton-dragging logic gates

The timing restrictions for soliton-dragging logic gates can be relaxed by asymmetrizing the interaction between the orthogonally polarized control and signal pulses. In particular, by prechirping the signal pulse in a normal group-velocity dispersion fiber, we find experimentally that the timing restriction can be loosened from less than 2 pulse widths to over 3.3 pulse widths. For this passive prechirper arrangement the timing restrictions are loosened at the expense of increased minimum switching energy. Soliton-dragging logic gates with a signal prechirper can provide timing restoration as well as logic-level restoration, so that two inverter gates can be cascaded to implement an ultrafast, all-optical pulse regenerator.