Implementation of a fiber-optic delay-line memory

The construction and operation of a 50-MHz 64 x 16 bit fiber-optic bit-serial delay-line memory is described. It consists of LiNbO(3) directional coupler switches, fused-fiber couplers, and a 4.17-km fiber loop. It is a subsystem of a bit-serial optical computer under construction by our group. We discuss delay and clock source stability requirements for the long delay line in the face of a limited phase error tolerance. The reliability testing of the memory subsystem is described. The degradation of data in the memory loop as the phase error tolerance is exceeded by a small amount is studied through the temperature dependence of the memory loop. Data are presented for the memory-loop stability with respect to temperature variations. The memory subsystem design and construction is presented. The results of these experiments support the feasibility of a 100-MHz 128 x 16 bit memory.