A subthreshold aVLSI implementation of the Izhikevich simple neuron model

Area of Science:

• Neuroscience
• Electrical Engineering
• Computational Neuroscience

Background:

• The Izhikevich neuron model offers a versatile framework for simulating diverse neural dynamics.
• Efficient hardware implementation of neuron models is crucial for large-scale neural simulations and bioelectronic devices.

Purpose of the Study:

• To present a compact analog Very-Large-Scale Integration (VLSI) circuit architecture for the Izhikevich neuron model.
• To achieve high energy efficiency and replicate various neural spiking and bursting dynamics.

Main Methods:

• Utilized log-domain circuit design with Metal-Oxide-Semiconductor (MOS) transistors operating in subthreshold.
• Implemented the two-state variable and four-parameter Izhikevich neuron equations in analog circuitry.
• Analyzed the impact of parameter variations on the model's dynamics.

Main Results:

• Achieved a compact analog VLSI implementation of the Izhikevich neuron model.
• Demonstrated high energy efficiency, consuming less than 1 picojoule (pJ) per spike.
• Simulation results successfully replicated several types of neural dynamics, including spiking and bursting patterns.

Conclusions:

• The proposed low-power, compact analog VLSI architecture is suitable for neural prostheses and implantable bioelectronics.
• This design serves as a valuable tool for large-scale neural emulation in computational neuroscience research.