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Updated: Jun 6, 2026

Optimized Fabrication Procedure for High-Quality Graphene-based Moiré Superlattice Devices
Published on: July 11, 2025
Peak channel temperature of graphene-based transistors
Geunwoo Ko1, Younghun Jung, Jihyun Kim
1Department of Chemical and Biological Engineering, Korea University, Seoul 136-701, Korea.
Abstract:
In this study, graphene was mechanically deposited on SiO2/Si substrate, followed by ohmic metallization using electron-beam lithography. Finite element analysis was employed to characterize the operating temperature of graphene-based devices using the experimentally determined current-voltage data. The temperature of the hottest spot where the underlying SiO2 layer was 300 nm thick was elevated up to about 70 degrees C at a 10 mW dissipated power. However, the operating temperature dropped to about 50 degrees C when the 300 nm thick SiO2 layer was replaced with a 20 nm thick SiO2 layer. Thermal management is very critical in the reliability of graphene-based high speed electronic devices because the high operating temperature can degrade the device performance.
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