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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Giant piezoresistance of p-type nano-thick silicon induced by interface electron trapping instead of 2D quantum
1State Key Laboratory of Transducer Technology, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, People's Republic of China.
Abstract:
The p-type silicon giant piezoresistive coefficient is measured in top-down fabricated nano-thickness single-crystalline-silicon strain-gauge resistors with a macro-cantilever bending experiment. For relatively thicker samples, the variation of piezoresistive coefficient in terms of silicon thickness obeys the reported 2D quantum confinement effect. For ultra-thin samples, however, the variation deviates from the quantum-effect prediction but increases the value by at least one order of magnitude (compared to the conventional piezoresistance of bulk silicon) and the value can change its sign (e.g. from positive to negative). A stress-enhanced Si/SiO(2) interface electron-trapping effect model is proposed to explain the 'abnormal' giant piezoresistance that should be originated from the carrier-concentration change effect instead of the conventional equivalent mobility change effect for bulk silicon piezoresistors. An interface state modification experiment gives preliminary proof of our analysis.
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