Experimental study on the subthreshold swing of silicon nanowire transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I(ON)) and off-current (I(OFF)) of the fabricated silicon nanowire FET are 0.59 microA and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mV/V respectively due to the 30 nm thick gate oxide and 10(15) cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.