Programmable nanowire circuits for nanoprocessors.

Area of Science:

• Nanoelectronics and Nanotechnology
• Materials Science
• Computer Engineering

Background:

• Existing nanoelectronic circuits face limitations in scalability and functionality for complex nanoprocessors.
• Previous efforts with nanowires and carbon nanotubes achieved simple logic gates but lacked complexity and integration.
• Memristor arrays offer limited cascading capabilities due to their passive nature.

Purpose of the Study:

• To design, fabricate, and demonstrate programmable and scalable logic tiles for advanced nanoprocessors.
• To overcome material, assembly, and architectural challenges in nanoscale circuit development.
• To enable the creation of multifunctional nanoelectronic systems with integrated computing and memory.

Main Methods:

• Fabrication of non-volatile field-effect transistors (FETs) using Ge/Si core/shell nanowires with programmable threshold voltages.
• Development of a tiled architecture integrating 496 functional configurable FET nodes within a compact area (∼960 μm²).
• Programming and operation of the logic tile as various logic functions, including full adder, full subtractor, multiplexer, demultiplexer, and D-latch.

Main Results:

• Demonstrated single-nanowire FETs with uniform, programmable threshold voltages capable of driving cascaded elements.
• Successfully programmed a single logic tile to perform multiple complex logic functions (full adder, subtractor, multiplexer, etc.).
• Achieved a maximal voltage gain of ten and input-output voltage matching in the full adder configuration.

Conclusions:

• The developed programmable logic tiles represent a significant advancement in complexity and functionality for bottom-up nanoelectronic circuits.
• The tiled architecture facilitates scalability and cascading, paving the way for fully integrated nanoprocessors.
• This work enables nanoprocessors with combined computing, memory, and addressing capabilities for future nanosystems.