Top-gated graphene field-effect transistors with high normalized transconductance and designable dirac point voltage

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Graphene field-effect transistors (G-FETs) are promising for advanced electronics.
• Achieving high carrier mobility and efficient gate control in G-FETs remains a challenge.
• Optimizing gate dielectric properties is crucial for device performance.

Purpose of the Study:

• To fabricate high-performance G-FETs with enhanced carrier mobility and top-gate efficiency.
• To investigate the impact of gate dielectric quality on G-FET characteristics.
• To demonstrate the designability of Dirac point voltage in G-FETs.

Main Methods:

• High-quality Yttrium Oxide (Y2O3) gate oxide was grown at high oxidizing temperatures.
• Fabrication of G-FETs with optimized Y2O3 dielectric layers.
• Characterization of device performance, including carrier mobility, transconductance, and Dirac point voltage.

Main Results:

• Achieved carrier mobility up to 5400 cm²/V·s and top-gate efficiency up to 120.
• Normalized transconductance reached 7900 μF/V·s, among the highest reported for G-FETs.
• Demonstrated tunable Dirac point voltage by selecting gate metals (e.g., Ti, Pd) with different work functions.

Conclusions:

• High-quality Y2O3 gate oxide enables simultaneous high carrier mobility and gate efficiency in G-FETs.
• The study highlights the potential for designing G-FETs with specific operating characteristics.
• Further improvements in G-FET performance are limited by series resistance, suggesting future research directions.