A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

Area of Science:

• Materials Science
• Semiconductor Physics
• Electrical Engineering

Background:

• Capacitor-less memory cells offer a path to higher memory densities.
• Strained silicon technology can enhance transistor performance.
• Fully depleted silicon-on-insulator (FD SOI) technology provides electrostatic control.

Purpose of the Study:

• To fabricate and characterize a multi-level capacitor-less memory cell using a nano-scale strained silicon channel.
• To investigate the impact of biaxial tensile strain on electron mobility in FD SOI n-MOSFETs.
• To demonstrate the feasibility of high-level volatile memory operation.

Main Methods:

• Fabrication of a fully depleted n-metal-oxide-semiconductor field-effect transistor (FD n-MOSFET) on a nano-scale strained silicon channel on insulator (sSOI).
• Application of 0.73% biaxial tensile strain to the silicon channel.
• Characterization of memory cell operation using both front- and back-gate biasing.
• Evaluation of retention time and memory margin for multi-level operation.

Main Results:

• The strained silicon channel enhanced effective electron mobility by approximately 1.7 times compared to unstrained silicon.
• Demonstrated eight-level volatile memory-cell operation.
• Achieved a retention time of 1 ms and a memory margin of 12 µA.
• Successful front- and back-gate cell operations were confirmed.

Conclusions:

• Nano-scale strained silicon channels in FD SOI n-MOSFETs are effective for high-performance capacitor-less memory cells.
• The enhanced electron mobility directly translates to improved memory characteristics.
• This work represents a significant step towards achieving terabit-scale volatile memory cells.