A VLSI Systolic Architecture for Pattern Clustering.

Area of Science:

• Computer Science
• Electrical Engineering
• Data Science

Background:

• Cluster analysis is crucial for exploratory data analysis and unsupervised pattern recognition.
• Squared-error clustering is a popular but computationally intensive technique, demanding significant CPU time.
• Advances in VLSI technology enable hardware implementation of complex algorithms.

Purpose of the Study:

• To propose a hardware implementation for squared-error clustering using a two-level pipelined systolic array.
• To design efficient memory storage and access schemes for optimized data flow.
• To evaluate the performance and suitability of the proposed architecture for VLSI.

Main Methods:

• Development of a two-level pipelined systolic pattern clustering array architecture.
• Design of memory storage and access schemes for rhythmic data flow.
• Performance evaluation through simulation experiments and architectural configuration analysis.

Main Results:

• The proposed systolic array architecture achieves enhanced system performance through pipelined processing units.
• Memory schemes facilitate rhythmic data flow, minimizing data access bottlenecks.
• The architecture's modularity and regularity are well-suited for VLSI implementation.

Conclusions:

• The hardware-based pipelined systolic array offers a significant speedup for squared-error clustering.
• The design effectively addresses the computational demands of iterative clustering algorithms.
• This approach is highly suitable for VLSI implementation in pattern recognition and image segmentation.