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In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
Published on: May 13, 2020
Reduce cell to cell charge interference by virtual ground inclusion in 3-dimensional vertical gate NAND flash memory
Seonjun Choi1, Joonhyuk Lee, Seulki Oh
1Department of Electronic Engineering, Hanyang University, Seoul, 133-791, Korea.
Journal of Nanoscience and Nanotechnology
|November 30, 2011
Summary
Structural modifications to 3D vertical gate NAND flash memory, including barrier oxide structure (BOS) and virtual ground structure (VGS), significantly reduce charge interference. These innovations enhance memory cell performance by minimizing unwanted charge effects.
Area of Science:
- Semiconductor Device Physics
- Materials Science
- Electrical Engineering
Background:
- Charge interference in 3D vertical gate NAND flash memory cells degrades performance.
- Existing memory structures face challenges with charge leakage and crosstalk between adjacent cells.
Purpose of the Study:
- To propose and evaluate novel structural modifications for 3D vertical gate NAND flash memory.
- To mitigate charge interference issues in Oxide-Nitride-Oxide (ONO) trap layers.
- To enhance the reliability and performance of NAND flash memory devices.
Main Methods:
- Development of a barrier oxide structure (BOS) by inserting an oxide layer.
- Implementation of a virtual ground structure (VGS) using a highly p-type doped polysilicon layer.
- Investigation of current-voltage (I-V) characteristics using 3D Technology Computer-Aided Design (TCAD) simulations.
- Analysis of device performance with crystalline and polysilicon body types under single and double programming conditions.
Main Results:
- The barrier oxide structure (BOS) effectively blocks electron movement, reducing charge interference.
- The virtual ground structure (VGS) minimizes electric field variations caused by stored charge.
- Both BOS and VGS modifications demonstrated significant reductions in charge interference.
- These improvements were validated in both crystalline silicon and high-quality polysilicon body structures.
Conclusions:
- The proposed BOS and VGS modifications are effective solutions for charge interference in 3D vertical gate NAND flash memory.
- These structural changes enhance device reliability and performance, particularly in crystalline silicon and high-quality polysilicon.
- The findings contribute to the advancement of next-generation non-volatile memory technologies.
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