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Efficient phase unwrapping architecture for digital holographic microscopy.

Wen-Jyi Hwang1, Shih-Chang Cheng, Chau-Jern Cheng

  • 1Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117, Taiwan. whwang@csie.ntnu.edu.tw

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This study introduces a new phase unwrapping architecture for faster digital holographic microscopy (DHM). The hardware design speeds up computations and reduces resource usage for embedded DHM systems.

Keywords:
FPGAdigital holographic microscopyphase unwrappingreconfigurable computingsystem on programmable chip

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Area of Science:

  • Optics and Photonics
  • Microscopy
  • Digital Imaging

Background:

  • Digital holographic microscopy (DHM) is crucial for advanced imaging.
  • Phase unwrapping is a computationally intensive step in DHM.
  • Existing methods face challenges in speed and hardware efficiency.

Purpose of the Study:

  • To develop a novel, hardware-efficient phase unwrapping architecture for DHM.
  • To accelerate the computational speed of DHM systems.
  • To reduce hardware resource requirements for embedded DHM applications.

Main Methods:

  • Implemented a pipeline architecture for maximum computational throughput.
  • Utilized a Fast Fourier Transform (FFT)-based phase unwrapping algorithm for robustness and simplicity.
  • Minimized hardware multipliers and dividers to reduce costs.
  • Integrated the architecture into a System on Programmable Chip (SOPC) for performance measurement.

Main Results:

  • The proposed architecture significantly expedites computational speed in DHM.
  • Achieved low hardware resource consumption.
  • Demonstrated effectiveness in physical performance measurements.
  • The pipeline design maximizes data throughput.

Conclusions:

  • The novel architecture offers a significant advancement for accelerating DHM.
  • It provides an effective solution for low-resource, high-speed embedded DHM systems.
  • The FFT-based approach ensures robustness and efficiency.