Ultrasound array transmitter architecture with high timing resolution using embedded phase-locked loops.

Area of Science:

• Ultrasound imaging systems
• Signal processing

Background:

• Coarse time quantization of delay profiles in ultrasound arrays generates undesirable side lobes.
• Phase quantization error magnitude directly impacts side lobe severity.

Purpose of the Study:

• To present a novel method for enhancing interchannel delay accuracy in ultrasound systems.
• To mitigate side lobe generation without increasing system clock frequency.

Main Methods:

• Utilizing embedded phase-locked loop (PLL) components within field-programmable gate arrays (FPGAs).
• Achieving precise delays by adjusting relative phases of embedded PLL output clocks in 208-ps steps.
• Validating the architecture for ultrasound arrays up to 50 MHz and extrapolating to higher frequencies.

Main Results:

• The proposed method achieves necessary interelement timing resolution for high-frequency ultrasound arrays.
• Experimental results show an increase in transmit dynamic range (TDR).
• Accurate delay profiles generated by the embedded-PLL method outperform system clock-quantized profiles.

Conclusions:

• Embedded PLLs offer a viable solution for precise interchannel delay control in ultrasound systems.
• This technique effectively reduces side lobes and enhances TDR.
• The method is scalable to higher frequencies, demonstrating its broad applicability.