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Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking
Ashfaque Uddin1, Kaveh Milaninia, Chin-Hsuan Chen
1A. Uddin, K. Milaninia, C. -H. Chen, and L. Theogarajan are with the Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, 93106-9560 USA.
IEEE Transactions on Components, Packaging, and Manufacturing Technology
|March 9, 2012
Summary
This study introduces a new method for integrating small CMOS chips onto large substrates using self-aligned masking. This technique ensures precise alignment and preserves chip functionality for advanced applications like biosensing.
Area of Science:
- Materials Science and Engineering
- Electrical Engineering
- Microtechnology
Background:
- Integrating small complementary metal-oxide-semiconductor (CMOS) chips into larger substrates presents fabrication challenges.
- Existing methods often lack the precision required for advanced microelectronic and microelectromechanical systems (MEMS) applications.
Purpose of the Study:
- To present a novel technique for seamless integration of small CMOS chips into large-area substrates.
- To enable post-integration MEMS micromachining and the incorporation of macroscale components.
Main Methods:
- Utilized CMOS chip-based self-aligned masking for precise socket fabrication.
- Employed a bonding process on a carrier to ensure flush surfaces between chip and substrate.
- Demonstrated the technique by integrating a low-power potentiostat chip for biosensing.
Main Results:
- Achieved wafer sockets only 5 µm larger than the chip on each side.
- Measured a horizontal gap of 4 µm and vertical displacement of 0.5 µm post-integration.
- Successfully patterned 104 interconnects with high-precision alignment, maintaining chip functionality.
Conclusions:
- The proposed integration technique is effective for combining CMOS chips with large substrates.
- The method supports the integration of macroscale components and post-integration MEMS micromachining.
- The process does not compromise the electrical functionality of the integrated CMOS chips.
