CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing.

Area of Science:

• Integrated circuit design
• Quantum computing hardware
• Solid-state physics

Background:

• Intrinsically random hardware devices are crucial for probabilistic computing.
• Single-photon avalanche diodes (SPADs) and variable-rate SPAD circuits (VRSCs) are promising hardware random number generators.
• Previous work established VRSCs for sampling and annealing Ising and Potts models.

Purpose of the Study:

• To advance the understanding of VRSC designs for probabilistic computing.
• To explore design tradeoffs in SPADs and processing circuits for VRSCs.
• To evaluate VRSC performance in a 65-nm CMOS process.

Main Methods:

• Fabrication and characterization of multiple VRSC designs in a 65-nm CMOS process.
• Evaluation of three SPAD designs and three processing circuit types.
• Analysis of metrics including area, speed, variability, and transfer functions.

Main Results:

• Small SPADs are suitable for probabilistic computing, and high dark count rates are acceptable.
• SPADs for probabilistic computing are readily integrable into standard CMOS processes.
• New time-to-analog-based designs offer analytical transfer functions, while filter-based designs provide lower variability in smaller footprints.
• Fabricated probabilistic bits (P-bits) achieve 50 MHz bit flip rates and controllable simulated annealing temperatures.

Conclusions:

• VRSC design choices significantly impact performance metrics like area, speed, and variability.
• Optimized VRSCs offer a viable hardware solution for probabilistic computing applications.
• The study provides valuable insights for the design and integration of hardware random number generators in CMOS technology.