Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Experiment Videos

Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive

Snaider Carrillo1, Jim Harkin, Liam McDaid

  • 1Intelligent Systems Research Centre-ISRC, University of Ulster, Magee Campus, Londonderry BT48 7JL, Northern Ireland, United Kingdom. carrillo_lindado-s@email.ulster.ac.uk

Neural Networks : the Official Journal of the International Neural Network Society
|May 8, 2012
PubMed
Summary

Related Concept Videos

Neural Circuits01:25

Neural Circuits

Neural circuits and neuronal pools are two of the main structures found in the nervous system. Neural circuits are networks of neurons that work together to carry out a specific task or process. They consist of interconnected neurons and glial cells, which provide structural and metabolic support.
Neuronal pools are collections of nerve cells with similar functions and interact through chemical and electrical signals. These pools include both interneurons (the central neural circuit nodes that...

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

A Novel Pipeline for Adrenal Gland Segmentation: Integration of a Hybrid Post-Processing Technique with Deep Learning.

Journal of imaging informatics in medicine·2025
Same author

Mathematical Modeling of PI3K/Akt Pathway in Microglia.

Neural computation·2024
Same author

The influence of astrocytic leaflet motility on ionic signalling and homeostasis at active synapses.

Scientific reports·2023
Same author

Image-based computer modeling assessment of microwave ablation for treatment of adrenal tumors.

International journal of hyperthermia : the official journal of European Society for Hyperthermic Oncology, North American Hyperthermia Group·2022
Same author

Immuno-informatics analysis predicts B and T cell consensus epitopes for designing peptide vaccine against SARS-CoV-2 with 99.82% global population coverage.

Briefings in bioinformatics·2021
Same author

Mathematical modelling of human P2X-mediated plasma membrane electrophysiology and calcium dynamics in microglia.

PLoS computational biology·2021

This article introduces a new type of router for computer chips designed to mimic the human brain. By adjusting to data traffic in real-time, this router helps manage the complex connections needed for large-scale artificial neural systems, improving overall efficiency and reliability.

Area of Science:

  • Neuromorphic engineering within spiking neural network hardware research
  • Computer architecture and high-performance interconnect systems

Background:

Current computing architectures struggle to replicate the massive connectivity found in biological brains. Researchers face significant hurdles when attempting to scale artificial systems to match billions of neurons. No prior work had resolved the conflict between high interconnect density and power efficiency. That uncertainty drove the exploration of new hardware paradigms. Existing interconnection fabrics often fail to balance throughput requirements with limited power budgets. This gap motivated the development of specialized communication structures for neural emulation. Scientists seek to bridge the divide between biological efficiency and silicon-based performance. These challenges highlight the need for innovative routing strategies in modern hardware design.

Purpose Of The Study:

This study aims to develop a traffic-aware adaptive router to enhance connectivity in artificial neural systems. The researchers address the limitation of current hardware in providing sufficient density for billions of neurons. They seek to balance scalability, throughput, and power consumption within a unified framework. This work focuses on the EMBRACE architecture to emulate biological information processing principles. The team intends to overcome the challenges of packet loss in congested communication fabrics. They explore how adaptive behavior can improve the robustness of neural hardware implementations. This investigation seeks to provide a practical solution for large-scale spiking neural network deployment. The authors strive to demonstrate that their approach outperforms traditional methods in this specialized domain.

Keywords:
neuromorphic hardwarenetwork-on-chipadaptive routingdata congestion management

Frequently Asked Questions

The researchers propose a traffic-aware adaptive router that dynamically adjusts to congestion. This mechanism prevents packet loss during high-load scenarios, ensuring reliable communication between artificial neurons compared to static routing alternatives.

The EMBRACE architecture serves as the overarching framework for this system. It integrates the adaptive router to facilitate inter-neuron connectivity, distinguishing it from standard network-on-chip designs that lack neural-specific traffic management.

A 90 nm Complementary Metal-Oxide-Semiconductor technology is necessary to evaluate power and area performance. This specific fabrication process allows for a direct comparison against existing network-on-chip solutions in the neuromorphic domain.

The study utilizes a Stratix II Field-Programmable Gate Array to verify the router's adaptive behavior. This hardware platform provides a real-time environment to test how the system handles actual traffic congestion patterns.

Related Experiment Videos

Main Methods:

The authors employ a design-based review approach to evaluate their novel router architecture. They utilize 90 nm Complementary Metal-Oxide-Semiconductor fabrication for detailed performance modeling. The team conducts a comparative analysis against established interconnection fabrics. They implement a 4x2 router array on a Stratix II Field-Programmable Gate Array. This setup allows for the simulation of real-time traffic congestion scenarios. The researchers assess throughput metrics alongside power and area requirements. They validate the adaptive logic by monitoring packet delivery under varying load conditions. This methodology ensures a rigorous examination of the proposed hardware's capabilities.

Main Results:

The adaptive router demonstrates superior performance metrics compared to existing network-on-chip solutions. It effectively maintains communication integrity by adjusting to traffic congestion in real-time. The design successfully avoids dropped packets during high-load simulation scenarios. Performance analysis using 90 nm technology confirms improved throughput and power efficiency. The Field-Programmable Gate Array implementation verifies the router's functionality within a 4x2 array configuration. These results indicate that the system handles complex data patterns efficiently. The findings show that the proposed architecture meets the demands of large-scale neural emulation. This evidence supports the feasibility of integrating the router into embedded hardware platforms.

Conclusions:

The authors demonstrate that their adaptive router successfully manages data flow within the EMBRACE framework. This design maintains communication integrity by dynamically responding to congestion patterns. Their findings suggest that this approach effectively supports the dense connectivity required for large-scale neural emulation. The study confirms that the proposed hardware achieves superior performance compared to traditional alternatives. These results validate the use of traffic-aware mechanisms in future neuromorphic platforms. The implementation on field-programmable gate arrays proves the practical viability of the system. This work offers a scalable solution for building complex artificial neural systems. The synthesis of these findings highlights the potential for improved efficiency in brain-inspired computing hardware.

The authors measure throughput, power consumption, and silicon area. These metrics provide a comprehensive assessment of the router's efficiency, contrasting the proposed design's performance against conventional interconnection fabrics.

The researchers propose that their design enables the realization of large-scale spiking neural networks on embedded hardware. This implication suggests a path toward more efficient, brain-inspired computing platforms that overcome previous density limitations.