A novel 3D stacking method for Opto-electronic dies on CMOS ICs

Area of Science:

• Optoelectronics
• Integrated Circuits
• Materials Science

Background:

• Developing compact, high-speed transceiver modules is crucial for modern communication systems.
• Existing methods often face challenges in cost, density, and integration complexity.
• Bridging the height difference between opto-electronic and CMOS components is a key fabrication hurdle.

Purpose of the Study:

• To present a novel, cost-effective solution for fabricating compact transceiver modules.
• To demonstrate a technique for direct bonding of opto-electronic dies onto CMOS integrated circuits.
• To achieve high-speed and high-density performance in transceiver modules.

Main Methods:

• Directly bonding an opto-electronic die on top of a CMOS integrated circuit (IC) chip.
• Utilizing a photoresist ramp to bridge the significant height difference (approx. 220 μm) between pad levels.
• Employing a lithographical process for electrical interconnections, scalable to wafer-level production.

Main Results:

• Successful fabrication of a 12-channel transmitter module utilizing the described technique.
• Demonstrated good performance of the fabricated module at data rates up to 12.5 Gb/s per channel.
• The lithographical process proved scalable for full wafer production.

Conclusions:

• The presented direct bonding and photoresist ramp technique offers a viable, low-cost solution for compact transceiver modules.
• This method effectively addresses the integration challenges between opto-electronic and CMOS components.
• The achieved performance validates the potential of this approach for high-speed optical communication applications.