Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS

Tung-Chien Chen1, Tsung-Chuan Ma, Yun-Yu Chen

  • 1DSP/IC Design Lab, Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan. djchen@video.ee.ntu.edu.tw

Summary

This study introduces on-chip spike sorting with integrated interpolation hardware. This innovation improves accuracy and power efficiency, allowing lower sampling rates without performance compromise in neural recordings.

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