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Field Effect Transistor

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Field-effect transistors (FETs) are integral to electronic circuits and distinguished by their three-terminal setup: the gate, drain, and source. These transistors operate as unipolar devices, which utilize either electrons or holes as charge carriers, in contrast to bipolar transistors, which use both types of carriers. The primary function of the FET is to modulate the flow of these carriers from the source to the drain through a channel. The voltage difference between the gate and source...

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Related Experiment Video

Updated: May 14, 2026

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

Published on: June 18, 2013

Vertical nanowire array-based field effect transistors for ultimate scaling.

G Larrieu¹, X-L Han

¹LAAS, CNRS, Univ de Toulouse, 7 av. du Colonel Roche, 31077 Toulouse, France. glarrieu@laas.fr

|February 14, 2013

Summary

This summary is machine-generated.

Researchers developed high-performance vertical nanowire field-effect transistors. This scalable architecture overcomes limitations of current silicon devices, enabling smaller, low-power transistors and memory with reduced variability.

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Area of Science:

Materials Science
Electrical Engineering
Nanotechnology

Background:

Planar silicon transistors face scaling limits.
Nanowire field-effect transistors (FETs) offer potential for improved electrostatic control and reduced leakage.
Scalable and reproducible nanowire FET architectures with high electrical performance are needed.

Purpose of the Study:

To demonstrate a high-performance FET architecture using dense vertical nanowire arrays.
To address the need for scalable and reproducible nanowire FETs with excellent electrical properties.

Main Methods:

Fabrication of field-effect transistors on massively parallel dense vertical nanowire arrays.
Implementation of silicided source/drain contacts.
Use of scaled metallic gate length through a simple process.

Main Results:

Achieved high-performance field-effect transistors on vertical nanowire arrays.
Demonstrated improved immunity to short channel effects.
Reduced device-to-device variability.
Enabled nanometer gate length patterning without high-resolution lithography.

Conclusions:

The proposed vertical nanowire FET architecture is scalable and reproducible.
This architecture offers significant advantages for manufacturing low-power transistors and memory devices.
It overcomes limitations of current planar silicon electronics.