Reconfiguration-based implementation of SVM classifier on FPGA for Classifying Microarray data.

Area of Science:

• Bioinformatics
• Computer Engineering
• Computational Biology

Background:

• High-dimensional Microarray data classification demands significant computational power.
• Support Vector Machines (SVM) are effective but computationally intensive classifiers for Microarray analysis.
• Hardware acceleration can address the computational challenges of SVM algorithms.

Purpose of the Study:

• To present a flexible, dynamically and partially reconfigurable Field Programmable Gate Array (FPGA) implementation of an SVM classifier.
• To accelerate the classification of high-dimensional Microarray data using hardware-based SVM.
• To evaluate the performance enhancement of SVM on FPGAs for bioinformatics applications.

Main Methods:

• Developed a reconfigurable SVM architecture on an FPGA.
• Implemented SVM algorithm kernels to exploit hardware parallelism.
• Compared FPGA performance against general-purpose processors (GPPs).

Main Results:

• Achieved up to an 85x speed-up in Microarray data classification compared to GPPs.
• Demonstrated the feasibility of hardware acceleration for complex SVM algorithms.
• Showcased the effectiveness of FPGAs for high-dimensional data analysis.

Conclusions:

• FPGA-based SVM implementation significantly enhances computational performance for Microarray data analysis.
• FPGAs offer a viable solution for accelerating computationally demanding bioinformatics tasks.
• This approach paves the way for efficient hardware acceleration in future bioinformatics applications.