Related Experiment Video
Updated: May 6, 2026

09:49
In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
Published on: May 13, 2020
3.2K
Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory
Hong-Yu Chen1, Shimeng Yu, Bin Gao
1Center for Integrated Systems and Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA.
Nanotechnology
|October 24, 2013
Summary
Researchers explored vertical scaling in 3D resistive random access memory (RRAM) arrays. By reducing electrode thickness to 5 nm, they achieved a five-fold increase in device density for high-density data storage.
Area of Science:
- Materials Science and Engineering
- Electrical Engineering
- Nanotechnology
Background:
- The storage density of 3D vertical resistive random access memory (RRAM) cross-point arrays is critically dependent on the multi-layer stack thickness.
- Previous RRAM designs utilized thicker plane electrodes, limiting achievable device density and overall storage capacity.
Purpose of the Study:
- To investigate the vertical scaling potential of multi-layer stacked 3D RRAM cross-point arrays.
- To demonstrate experimentally the feasibility of significantly reducing electrode thickness for enhanced storage density.
Main Methods:
- Fabrication and characterization of a vertical RRAM cell with a reduced plane electrode thickness (tm) of 5 nm.
- Experimental demonstration of device scaling to minimize the overall 3D stack height.
- Projection of layer stacking capabilities based on lithographic parameters (F=26 nm) and stack thickness (T=21 nm).
Main Results:
- Successfully demonstrated a vertical RRAM cell with a 5 nm plane electrode thickness.
- Achieved an improvement factor of 5 in device density compared to previous 22 nm electrode designs.
- Projected a bit density of 72.8 nm²/cell with 37 stacked layers.
Conclusions:
- Vertical scaling by reducing electrode thickness is a viable strategy for increasing 3D RRAM storage density.
- The 5 nm electrode thickness represents a significant advancement in minimizing stack height and maximizing device density.
- This approach holds promise for future high-density non-volatile memory applications.

