Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory

Hong-Yu Chen1, Shimeng Yu, Bin Gao

  • 1Center for Integrated Systems and Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA.

Nanotechnology
|October 24, 2013
PubMed
Summary

Researchers explored vertical scaling in 3D resistive random access memory (RRAM) arrays. By reducing electrode thickness to 5 nm, they achieved a five-fold increase in device density for high-density data storage.

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