Dual-material-gate engineering for GIDL suppression and pillar aspect-ratio reduction in 4F²vertical DRAM cell...

Area of Science:

• Semiconductor device physics
• Advanced memory technology
• Materials science in electronics

Background:

• Scaling 4F² vertical DRAM presents challenges with gate-induced drain leakage (GIDL).
• Conventional GIDL suppression using long lightly doped drain (LDD) regions increases pillar height and aspect ratio.
• This limits the structural feasibility of advanced DRAM designs.

Purpose of the Study:

• To propose and evaluate a novel dual-material-gate (DMG) architecture for GIDL control in 4F² vertical DRAM.
• To demonstrate DMG as an electrostatic alternative to LDD extension.
• To assess the impact of DMG on device performance and structural constraints.

Main Methods:

• Implementation of a dual-material-gate (M1-M2-M1 configuration).
• Utilizing TCAD simulations calibrated with experimental data.
• Analyzing electrostatic potential, electric field distribution, and device parameters (OFF-state current, pillar height, retention).

Main Results:

• The DMG structure reduces the required LDD length from 13 nm to 7 nm.
• Total pillar height is decreased by 20% (from 60 nm to 48 nm).
• OFF-state current remains comparable, while current drivability and write recovery time are improved.
• Achieved data retention of 34.5 seconds with a practical design window.

Conclusions:

• The DMG architecture effectively suppresses GIDL without requiring extended LDD regions.
• DMG improves structural feasibility and performance metrics for 4F² vertical DRAM.
• Electrostatic gate engineering offers a viable pathway to decouple GIDL control from LDD extension in advanced DRAM.