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Device/Circuit co-design guide for passive memristor array with non-linear current-voltage behavior.

Seok-Jin Ham1, Jeong-Heon Kim, Kyeong-Sik Min

  • 1School of Electrical Engineering, Kookmin University, Seoul 136-702, Korea.

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|November 12, 2013
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Summary
This summary is machine-generated.

This study analyzes memristor non-linearity, finding the V(DD)/2 scheme effectively suppresses resistance loss in half-selected cells. This memristor circuit design offers significant current reduction compared to V(DD)/3.

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Area of Science:

  • Electrical Engineering
  • Materials Science

Background:

  • Memristor devices exhibit non-linear current-voltage (I-V) characteristics.
  • Non-linearity in memristors can impact the performance of half-selected cells in memory arrays.

Purpose of the Study:

  • To analyze the effect of memristor non-linearity on half-selected cells.
  • To compare the V(DD)/2 and V(DD)/3 voltage schemes for memristor-based memory.
  • To identify optimal conditions for suppressing resistance loss.

Main Methods:

  • Simulations were performed to analyze the current-voltage relationship of memristors.
  • The non-linear coefficient's impact on resistance loss was evaluated.
  • Performance metrics of V(DD)/2 and V(DD)/3 schemes were compared.

Main Results:

  • For the V(DD)/2 scheme, a non-linear coefficient greater than 8 suppresses unwanted resistance loss to below 10%.
  • The V(DD)/2 scheme reduces current consumption by two orders of magnitude compared to the V(DD)/3 scheme.
  • The V(DD)/2 scheme results in a slightly larger resistance change in half-selected cells than the V(DD)/3 scheme.

Conclusions:

  • The V(DD)/2 scheme is effective in mitigating resistance loss in half-selected memristor cells.
  • Memristor non-linearity is a critical factor in designing efficient memory arrays.
  • The V(DD)/2 scheme offers a significant advantage in power consumption for memristor applications.