Hardware-efficient low-power image processing system for wireless capsule endoscopy.

Area of Science:

• Biomedical Engineering
• Digital Signal Processing
• Embedded Systems

Background:

• Next-generation wireless endoscopy demands efficient data handling for improved diagnostics.
• Existing systems often face limitations in power consumption and memory usage.
• Real-time image processing is crucial for effective in-body data transmission.

Purpose of the Study:

• To design a hardware-efficient, low-power image processing system for wireless endoscopy.
• To develop a novel image compression technique suitable for embedded applications.
• To integrate forward error correction (FEC) for robust data transmission.

Main Methods:

• Design of a custom CMOS image sensor and dedicated image compressor.
• Implementation of an integer Discrete Cosine Transform (DCT) and adaptive Golomb-Rice entropy coding.
• Integration of a Forward Error Correction (FEC) encoder and radio data transmitter.
• Prototyping the system on a low-power 65-nm Field Programmable Gate Arrays (FPGA) chip.

Main Results:

• Achieved on-the-fly image compression using a novel, low-complexity entropy encoder.
• Significantly reduced memory requirements due to instant compression and FEC.
• Demonstrated low power consumption comparable to Application-Specific Integrated Circuits (ASICs).
• Successfully prototyped the system on a single FPGA chip.

Conclusions:

• The designed system offers a hardware-efficient, low-power solution for wireless endoscopy image processing.
• The novel compression and FEC techniques effectively address memory and transmission challenges.
• FPGA implementation provides a viable alternative to ASICs for power-constrained applications.