Leakage current behavior of the bottom gate poly thin-film transistor fabricated by copper damascene process

Bottom-gated polycrystalline-silicon (poly-Si) thin-film transistors (TFT's) with a planarized copper (Cu) gate for large-area displays have been fabricated and characterized. The 500 nm depth of trenchs are filled up with 400 nm, 500 nm, 600 nm thickness of Cu using the damascene process of VLSI technology, poly-Si TFT's with 100 nm thick gate insulator are fabricated on the Cu gate. As the Cu gate's thickness becomes thinner, the anomalous leakage current of poly-Si TFT's is reduced significantly both before and after electrical stressing. The results simulated by 3D electric field simulator demonstrate that the structure of planarized gate in bottom-gate TFT can effectively reduce the electric field causing the field emission between the gate and the drain.