Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

Area of Science:

• Medical Imaging
• Nuclear Instrumentation
• Semiconductor Devices

Background:

• Advancements in Silicon Photomultipliers (SiPMs) enable smaller, higher-resolution Positron Emission Tomography (PET) detectors.
• Increased detector density necessitates a greater number of channels for signal processing and image reconstruction.
• Existing readout electronics face challenges in managing the high channel count of dense SiPM arrays.

Purpose of the Study:

• To design a CMOS ASIC for signal reduction in readout electronics for an 8x8 SiPM array.
• To decrease the number of required channels for interfacing SiPMs with digital signal processing.
• To reduce the overall cost of digitizing electronics for high-resolution PET scanners.

Main Methods:

• Developed a CMOS ASIC featuring a row/column/diagonal summation circuit.
• Implemented current amplifiers for each SiPM cathode to reduce detector loading and extract addressing information.
• Integrated a Pulse-Positioning architecture for efficient extraction of timing data.
• Designed auxiliary components including a current-mode comparator and a variable output impedance I/O driver.

Main Results:

• The ASIC design significantly reduces the number of channels needed for an 8x8 SiPM array.
• The row/column/diagonal summation effectively minimizes readout complexity and cost.
• The Pulse-Positioning architecture enables simultaneous extraction of position and timing information.
• Designed components address dark noise reduction and adaptable interfacing with off-chip ADCs.

Conclusions:

• The developed CMOS ASIC offers a cost-effective solution for high-resolution PET detector readout.
• The signal reduction strategy is crucial for managing the increasing channel density in modern PET scanners.
• This ASIC design supports the advancement of PET technology towards more compact and efficient systems.