Application of butterfly Clos-network in network-on-chip

Area of Science:

• Computer Engineering
• Network Architecture
• VLSI Design

Background:

• Traditional Networks-on-Chip (NoC) face performance bottlenecks.
• Existing topologies like Clos and butterfly networks have limitations.

Purpose of the Study:

• To propose a novel hybrid topology, the Butterfly Clos-network (BFC), for Networks-on-Chip.
• To enhance NoC performance by integrating desirable features of Clos and butterfly networks.

Main Methods:

• A new topology, BFC, was designed by combining Clos and butterfly network characteristics.
• Modules within the same layer but different dimensions were integrated.
• Bidirectional links were employed for inter-module communication.
• Multistage routing utilizing intermediate nodes was implemented.

Main Results:

• The BFC network inherits the path diversity of the Clos network.
• Simulation analysis demonstrates superior throughput compared to the butterfly network.
• The BFC network exhibits reduced delay under congested traffic patterns.

Conclusions:

• The proposed BFC topology offers a promising solution for high-performance Networks-on-Chip.
• BFC effectively balances path diversity with improved throughput and reduced latency.
• This hybrid approach addresses key challenges in modern NoC design.