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Area of Science:

  • Electrical Engineering
  • Computer Engineering
  • Semiconductor Physics

Background:

  • Technology scaling reduces capacitance and voltage, increasing layout density and susceptibility to soft errors like single event upsets (SEUs).
  • Previous studies showed bias current injection improves SEU tolerance but increases power dissipation.

Purpose of the Study:

  • To investigate alternative methods for improving SEU tolerance in scaled technologies.
  • To evaluate the impact of transistor size and temperature on SEU tolerance.
  • To identify effective strategies for enhancing reliability with minimal power overhead.

Main Methods:

  • Testing the effect of varying transistor sizes on SEU tolerance.
  • Analyzing the influence of temperature on SEU tolerance.
  • Comparing SEU tolerance under different bias current conditions.

Main Results:

  • Increasing effective transistor length by 10% showed no significant change in critical charge (Q(crit)).
  • High temperature combined with high bias currents improved Q(crit), attributed to temperature-dependent process parameters.
  • No clear direct correlation was found between temperature and SEU tolerance.

Conclusions:

  • High bias currents remain the most effective method for improving SEU sensitivity.
  • Temperature does not appear to be a direct, independent factor influencing SEU tolerance.
  • A trade-off between reliability and power consumption is necessary for low-swing drivers to meet targets.