Neural CMOS-integrated circuit and its application to data classification.

Area of Science:

• Integrated Circuit Design
• Machine Learning Hardware
• Digital Signal Processing

Background:

• The need for efficient hardware classifiers is growing in various applications.
• Existing classifiers often face limitations in speed, power consumption, or adaptability.
• Tunable classifier core-cells offer a promising solution for flexible and high-performance classification.

Purpose of the Study:

• To implement and test a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) classifier core-cell (CC).
• To evaluate the performance of the CC using two different machine learning algorithms for parameter tuning.
• To demonstrate the application of the tunable CC in classifying benchmark datasets.

Main Methods:

• Implementation of a tunable classifier core-cell (CC) using CMOS AMS 0.35-μm technology.
• Utilizing Fisher's linear discriminant analysis and perceptron learning algorithms to determine CC tunable parameters.
• Hard-classification of the Haberman and Iris datasets using a neural network structured circuit with the obtained parameters.

Main Results:

• The tunable CC achieved a 6-ns response time and 1.8-mW power consumption.
• Classification performance and coefficient calculation times were evaluated for both tuning algorithms.
• Successful classification of the Haberman and Iris datasets was demonstrated.

Conclusions:

• The presented tunable CMOS-IC CC offers a high-speed and low-power solution for hardware-based classification.
• The choice of algorithm for parameter tuning impacts classification performance and computation time.
• The developed CC is suitable for efficient implementation of neural network classifiers.