Graphene/Si CMOS hybrid hall integrated circuits.

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Graphene's high carrier mobility and silicon CMOS's sophisticated functions offer potential for advanced integrated circuits.
• Integrating these heterogeneous materials on a single chip presents significant fabrication challenges.

Purpose of the Study:

• To develop a low-temperature process for integrating graphene devices onto silicon CMOS integrated circuits (ICs).
• To demonstrate a high-performance graphene/CMOS hybrid Hall integrated circuit (IC).

Main Methods:

• Silicon CMOS signal amplifying/processing ICs were manufactured using commercial 0.18 µm CMOS technology.
• Graphene Hall elements (GHEs) were fabricated on the passivation layer of the CMOS chip using a low-temperature micro-fabrication process.
• GHEs were integrated with CMOS amplifiers to enhance sensitivity.

Main Results:

• A novel low-temperature process successfully integrated graphene devices with silicon CMOS ICs.
• A high-performance graphene/CMOS hybrid Hall IC was demonstrated, showing improved sensitivity through integration with CMOS amplifiers.
• The fabricated hybrid ICs exhibit significantly higher performance compared to conventional Hall ICs.

Conclusions:

• This work establishes a scalable method for integrating graphene devices with silicon CMOS ICs using a low-temperature process.
• The developed hybrid Hall ICs offer superior performance, paving the way for next-generation sensing technologies.
• This approach enables the creation of advanced graphene/silicon CMOS hybrid ICs with enhanced functionalities.