Nanoscale carrier multiplication mapping in a Si diode.

Area of Science:

• Semiconductor Physics
• Materials Science
• Surface Science

Background:

• Carrier multiplication (CM) is a process where one high-energy electron generates multiple electron-hole pairs.
• Understanding CM is crucial for improving solar cell efficiency and other optoelectronic devices.
• Previous studies often lacked direct measurement of both electron and hole currents, limiting quantum yield determination.

Purpose of the Study:

• To investigate carrier multiplication in a silicon p-n junction.
• To directly measure electron and hole currents for unambiguous quantum yield determination.
• To spatially map the carrier multiplication efficiency and identify factors influencing it.

Main Methods:

• Utilized multiple probe scanning tunneling microscopy (STM) for high-resolution surface analysis.
• Employed STM to inject hot tunneling electrons and measure generated electron and hole currents.
• Performed spatial mapping of carrier multiplication efficiency across the silicon p-n junction surface.

Main Results:

• Achieved unambiguous determination of quantum yield by directly measuring electron and hole currents.
• Visualized the interplay of impact ionization, carrier diffusion, and recombination through spatial mapping.
• Identified atomically well-ordered surface areas as regions with the highest carrier multiplication rates.

Conclusions:

• The silicon p-n junction surface plays a critical role in achieving high carrier multiplication yields.
• Surface quality and atomic ordering are key factors for efficient carrier multiplication.
• The findings provide insights for designing advanced semiconductor devices with enhanced performance.