Analysis on multiple-component synchronization of ultra-fast time-interleaved analog-to-digital conversion systems and its novel parameterized hardware solution

Parallelism-based technique of time-interleaved analog-to-digital conversion (TIADC) has become an effective solution for the higher sampling rate acquisition system to acquire non-repetitive waveforms. With the increase of sampling frequency, the indeterminacy of combining sequence of sampled data among multiple components has become a highlighted barrier for the reset operation of high-speed acquisition systems, and this is especially obvious for the ultra-fast TIADC systems. In this paper, we clarify the root of the problem in multiple-component synchronization (MCS) caused by such reset operation. Also we propose a novel and reliable hardware solution to precisely condition each reset signal, including three key circuit design parameters, i.e., the best time interval, required edge uncertainty, and the minimum delay precision. Besides, the designing scheme and debugging procedures are presented in detail in a generalized platform of this system type. Finally, in order to demonstrate the feasibility, parametric materialization and testing verification are gradually accomplished in a 20 Giga Samples Per Second (GSPS) TIADC system composed of four 5 GSPS ADC components. The results show that the proposed method is feasible and effective for ensuring the combined determinacy of multiple groups of sampled data and solving the MCS problem. In comparison with other existing solutions, it adopts some simple logic components more easily and flexibly, and this is significant for the development of congeneric systems or instruments featuring the MCS.