Complexity optimization and high-throughput low-latency hardware implementation of a multi-electrode spike-sorting...

Area of Science:

• Neuroscience
• Biomedical Engineering
• Computer Science

Background:

• Real-time spike sorting is critical for understanding neural dynamics and developing brain-machine interfaces (BMIs).
• Existing algorithms struggle with the high data throughput and computational demands of large-scale, high-density neural recordings.
• Large electrode arrays (thousands of electrodes) require significant hardware resources for processing and data transmission.

Purpose of the Study:

• To develop computational complexity optimization techniques for spike-sorting algorithms.
• To adapt these techniques for large multi-electrode recording systems.
• To present a high-performance VLSI hardware architecture for real-time, low-latency spike sorting.

Main Methods:

• Computational complexity optimization applied to a previously published spike-sorting algorithm.
• Design of a reconfigurable, folded VLSI hardware architecture.
• Focus on transmitting only essential data like spike timestamps and waveforms.

Main Results:

• Optimized algorithms are now suitable for large electrode set recordings.
• The presented VLSI architecture processes hundreds of neurons in real-time with low latency.
• The system is adaptable to non-stationary neural recordings and reduces data bandwidth requirements.

Conclusions:

• The developed techniques and hardware architecture significantly improve the feasibility of real-time spike sorting for large-scale neural recordings.
• This advancement supports more sophisticated neural network dynamics studies and enhances BMI capabilities.
• Reduced data transmission and storage offer practical benefits for high-throughput neural data acquisition.