Break-before-make CMOS inverter for power-efficient delay implementation | JoVE Visualize

Area of Science:

Electrical Engineering
Computer Engineering
Microelectronics

Background:

Static CMOS inverters suffer from short-circuit current, leading to power overhead, especially when slower operation is required.
Minimizing short-circuit current is crucial for enhancing power efficiency in digital circuits.
Existing designs may not adequately address power reduction for specific operational speeds.

Purpose of the Study:

To propose a modified static CMOS inverter design that effectively reduces short-circuit current.
To enhance energy efficiency and reduce power overhead in circuits demanding slower operation.
To introduce a novel bidirectional delay element for improved dynamic response and reduced direct-path current.

Main Methods:

A modified static CMOS inverter incorporating a bidirectional delay element in series with switching transistors was designed.
Circuit simulations were performed to characterize various delay element implementations.
A global optimization procedure was employed for power-efficient transistor sizing.
The modified inverter chain's performance was compared against standard implementations across different delay settings.

Main Results:

The proposed modified CMOS inverter significantly reduces short-circuit current by ensuring switching transistors are never simultaneously ON.
Circuit simulations verified the effectiveness of the bidirectional delay element in managing dynamic response.
Transistor sizing optimization resulted in power-efficient configurations.
The modified inverter chain demonstrated up to a 40% reduction in energy (charge) per delay compared to standard designs.

Conclusions:

The modified static CMOS inverter with a bidirectional delay element offers a viable solution for reducing short-circuit current and power consumption.
This design is particularly beneficial for applications requiring controlled, slower operational speeds.
The proposed approach enables significant energy savings and is demonstrated through practical implementations like low-power delay lines and leading-edge detector cells.