A high speed CMOS image sensor with a novel digital correlated double sampling and a differential difference...

Area of Science:

• Electrical Engineering
• Computer Engineering
• Solid-state Physics

Background:

• CMOS image sensors (CIS) are crucial for digital imaging, but their operating speed is often limited by noise reduction techniques.
• Conventional digital correlated double sampling (CDS) methods, while effective for reducing fixed pattern noise (FPN), typically employ slower analog-to-digital converters (ADCs).
• The use of a single-slope ADC with separate ramps for reset and pixel signals in traditional digital CDS contributes to lower operating speeds compared to analog CDS.

Purpose of the Study:

• To develop a novel digital correlated double sampling (CDS) technique for CMOS image sensors (CIS) that enhances operating speed.
• To address the speed limitations inherent in conventional digital CDS methods by proposing a new circuit architecture.
• To demonstrate a significant improvement in frame rates for VGA resolution CIS devices.

Main Methods:

• A novel digital CDS technique is proposed, utilizing a differential difference amplifier (DDA).
• The DDA compares the reset and pixel signals using a single ramp, optimizing the conversion process.
• A prototype CIS with VGA resolution (640 × 480) was fabricated using 0.13 µm CIS technology.

Main Results:

• The proposed digital CDS technique achieves a conversion time of 16 µs.
• The fabricated prototype CIS demonstrates a high frame rate of 131 fps at VGA resolution.
• The DDA-based approach effectively reduces noise while increasing operational speed.

Conclusions:

• The novel DDA-based digital CDS technique offers a significant advancement in CIS operating speed.
• This method overcomes the speed bottleneck associated with conventional single-slope ADC-based digital CDS.
• The achieved high frame rate makes the developed CIS suitable for high-speed imaging applications.