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A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications
1Department of Electronics and Communication Engineering, PSNA College of Engineering and Technology, Dindigul 624622, India.
Thescientificworldjournal
|June 12, 2015
Summary
This study introduces an efficient Low-Density Parity-Check (LDPC) decoder architecture designed for low power consumption. The novel design reduces power usage and hardware requirements in modern wireless communication systems.
Area of Science:
- Electrical Engineering
- Computer Science
- Information Theory
Background:
- Low-Density Parity-Check (LDPC) codes are crucial in modern communication standards like WiMax and 4G.
- Efficient decoder architectures are needed to meet low-power application demands.
Purpose of the Study:
- To propose a highly efficient LDPC decoder architecture optimized for low power consumption.
- To analyze the impact of Euclidean orthogonal generators on error rate reduction.
Main Methods:
- Design and analysis of check node and variable node units.
- Integration of a Euclidean orthogonal generator within the LDPC decoder architecture.
- Synthesis and simulation on Xilinx 9.2i and Modelsim for 45 nm devices.
Main Results:
- The proposed LDPC decoder architecture demonstrates significant reductions in power consumption.
- Hardware utilization is substantially decreased compared to conventional architectures.
- The Euclidean orthogonal generator effectively reduces the error rate.
Conclusions:
- The developed LDPC decoder architecture offers a superior solution for low-power applications.
- This design contributes to more efficient and reliable wireless communication systems.
- The integration of Euclidean orthogonal generators enhances LDPC decoder performance.
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