Histogram-Based Calibration Method for Pipeline ADCs.

Area of Science:

• Electrical Engineering
• Signal Processing
• Integrated Circuit Design

Background:

• Traditional histogram-based calibration for analog-to-digital converters (ADCs) is data-intensive and time-consuming, particularly for high-resolution systems.
• Pipelined ADCs present unique calibration challenges due to inter-stage dependencies.

Purpose of the Study:

• To propose a fast and accurate calibration method for pipelined ADCs.
• To reduce the data volume and test duration required for ADC calibration.

Main Methods:

• A novel calibration method employing histograms generated from the output of each stage.
• Error sources are calculated based on the information derived from stage output histograms.
• The method leverages the dependency of digitized outputs on preceding stages to infer errors.

Main Results:

• Significant reduction in required samples and calibration time.
• For a 14-bit pipelined ADC, integral non-linearity (INL) improved from 6.78 to 0.52 LSB.
• Spurious-free dynamic range (SFDR) improved from 67.0 to 106.2 dB, and signal-to-noise-and-distortion ratio (SNDR) improved from 65.6 to 84.8 dB.

Conclusions:

• The proposed histogram-based calibration method offers a substantial improvement in speed and accuracy for pipelined ADCs.
• This technique effectively addresses the limitations of traditional methods for high-resolution ADC calibration.
• The implemented simple modules facilitate efficient error source calculation and performance enhancement.