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Biasing of Metal-Semiconductor Junctions

Biasing of Metal-Semiconductor Junctions

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Related Experiment Video

Updated: Jan 10, 2026

Tuning Oxide Properties by Oxygen Vacancy Control During Growth and Annealing

Tuning Oxide Properties by Oxygen Vacancy Control During Growth and Annealing

Published on: June 9, 2023

Effects of Annealing Temperature Combinations in InO_x/AlO_x Heterostructure for High-Performance and Stable

Jinhong Park¹, Dohyeon Gil¹, Se Jin Park¹

¹School of Electronic and Electrical Engineering, Kyungpook National University, 80 Daehakro, Bukgu, Daegu 41566, Republic of Korea.

Materials (Basel, Switzerland)

|November 27, 2025

Summary

High-temperature annealing of indium oxide and aluminum oxide layers in junctionless transistors significantly improves device performance and bias stability. This process is key for reliable, high-performance oxide electronics.

Keywords:

junctionless thin-film transistors metal-oxides positive bias instability thermal annealing

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Last Updated: Jan 10, 2026

Tuning Oxide Properties by Oxygen Vacancy Control During Growth and Annealing

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Published on: June 9, 2023

The Effect of Anodization Parameters on the Aluminum Oxide Dielectric Layer of Thin-Film Transistors

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Published on: May 24, 2020

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy

Published on: October 23, 2018

Area of Science:

Materials Science
Electrical Engineering
Semiconductor Physics

Background:

Junctionless thin-film transistors (JL TFTs) offer potential for low-cost, large-area electronics.
Enhancements in mobility and bias stability are crucial for JL TFT advancement.

Purpose of the Study:

To investigate the impact of annealing temperatures on indium oxide (InO_x) and aluminum oxide (AlO_x) layers in heterostructure JL TFTs.
To optimize the performance and reliability of InO_x/AlO_x JL TFTs through controlled annealing.

Main Methods:

Fabrication of InO_x/AlO_x heterostructure JL TFTs using solution deposition and photopatterning.
Independent annealing of InO_x and AlO_x layers at 250 °C and 400 °C.
Electrical characterization to assess device performance and bias stability.

Main Results:

Higher annealing temperature (400 °C) led to InO_x crystallization and densification.
Reduced metal-hydroxyl content in AlO_x at 400 °C annealing.
JL TFTs annealed at 400 °C showed superior electrical performance (mobility: 1.57 cm² V^-1 s^-1) and excellent bias stability (V_th shift: 1.70 V).

Conclusions:

Simultaneous high-temperature annealing of the channel and capping layer is vital for reducing trap-assisted scattering.
Optimized annealing stabilizes electrostatics, leading to enhanced bias stability in JL TFTs.
This study provides practical guidelines for developing high-performance, bias-stable oxide electronics.